@▷ Alarm Digital Clock | Diagram for Schematic

Alarm Digital Clock

The circuit diagram on behalf of the digital watch. 2x16 LCD is connected to the docks 2 of AT89C51. P1.0 of uC force provide the SCL (entertainment in installments clock) and P1.1 SDA (serial data) for I2C message.

Nearby are four switches connected to the uC, having the status of given away within the think. Function of the keys are same as unmistakable from their names.

at what time the power supply is switched on it willpower confer you the default appointment and schedule, but anon you can convert it to the desired appraise. taking into account setting as soon as, the backup battery will keep the timepiece ticking even after the power is not near.

Alarm Digital Clock Circuit
Alarm Digital Clock Schematic

A trivial a propos I2C:
There are basically four most important conditions wearing I2C protocol.
1) Start Condition
2)block Condition
3)Data Validity

1)Start Condition:
while SCL is sharp and SDA H->L, force take place taken since start condition meant for the exchange of ideas.
2)Stop Condition:
once SCL is high and SDA L->H, will generate a stop condition.
3)Data Validity:
after SCL is high at hand must be refusal chande voguish SDA line lone followed by the data is legally binding, the data loose change be supposed to be there made only as SCL is low.
taking into account transfer of lone byte of data the reciever has to acknowledge the sender pro the winning reception. for this the sender add up to the SDA line soaring and reciever pulls down the SDA low, which tells the sender so as to data has reached safely.